T5_EVENT0	Parameter Measured - Profiling Hardware Counters
0	Cycles
1	Issued instructions
2	Issued loads
3	Issued stores
4	Issued store conditionals
5	Failed store conditionals
6	Decoded branches
7	Quadwords written back from scache
8	Correctable scache data array ECC errors
9	Primary instruction cache misses
10	Secondary instruction cache misses
11	Instruction misprediction from scache way prediction table
12	External interventions
13	External invalidations
14	Virtual coherency conditions
15	Graduated instructions
16	Graduated cycles
17	Graduated instructions
18	Graduated loads
19	Graduated stores
20	Graduated store conditionals
21	Graduated floating point instructions
22	Quadwords written back from primary data cache
23	TLB misses
24	Mispredicted branches
25	Primary data cache misses
26	Secondary data cache misses
27	Data misprediction from scache way prediction table
28	External intervention hits in scache
29	External invalidation hits in scache
30	Store/prefetch exclusive to clean block in scache
31	Store/prefetch exclusive to shared block in scache