The Sequent Symmetry  is a bus-based, shared memory multiprocessor that can be configured with up to 30 processors. The Symmetry architecture provides hardware cache consistency through a copy-back policy and user-accessible hardware locking mechanisms for synchronization. For our prototype implementation, we used a Symmetry S81 machine with 24 processors (16 MHz Intel 80386 with a Weitek 1167 floating point coprocessor) and 256 MBytes of memory across four memory modules interleaved in 32 byte blocks.
Using Sequent's parallel programming library, the implementation of the pC++ runtime system was straightforward. Because all memory in the Sequent machine is physically shared in the hardware, the local allocation of the collection element tables on each processor is only meaningful relative to the virtual memory space of the process. All collection element tables are allocated in the local data segment of each process, making them readable only by the process that created them. In contrast, collection elements must be allocated in a shared segment of the virtual address space of each process; a shared memory allocation routine is used for this purpose. Unfortunately, there is no way to control the caching policy in software; copy-back is the hardware default. Barrier synchronization is implemented using a system-supplied barrier routine which takes advantage of the hardware locking facilities of the Sequent machine. It is very efficient - the barrier performance on 8, 12, 16, and 20 processors is 34, 47, 58, and 70 microseconds, respectively.