CIS PhD student Gravelle receives A. Richard Newton Young Student Fellow Award
CIS first-year PhD student Brian Gravelle was awarded the A. Richard Newton Young Student Fellow Award in April 2016. This award was set up to honor the memory of A. Richard Newton, a pioneer in electronic design automation and integrated circuit design.
The fellowship encourages and supports students at the beginning of their research career in Electronic Design Automation and Embedded Systems by providing them financial support to attend Design Automation Conference (DAC) and present their work. DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). With these awards, Brian Gravelle will have the opportunity to participate in numerous activities during the conference, including meetings with design automation luminaries, attendance at technical sessions and exhibits.
Brian's research focus is secure and energy-efficient architecture designs. He is leading our research group efforts on designing a hardware-software co-design computer platform for binary code and runtime obfuscation. The exponential growth of core count per chip coupled with the “dark silicon” problem, i.e., large portions of silicon are idle for long periods of time or significantly under-clocked at the nominal operating voltage to stay within the power budget, has intensified the need for robust and efficient dynamic power management schemes.
Brian will be presenting at DAC an efficient and practical algorithm, named COPAL (COnnectivity Preserving Algorithm), to identify routers, that will cause network disconnection in an off position, based on a distributed depth-first search (DFS) through "neighbor-to-neighbor" communication. The algorithm allows the runtime system to make effective power-gating decisions in on-chip network based systems. For an N-node network, the time complexity of COPAL is O(N) and the total number of messages sent in classifying nodes’ criticality in optimizing network connectivity is in the order of 2Nlog2(N). FPGA implementation shows that the algorithm is scalable and the required hardware resource overhead is minimal.