The problem of loading (unloading) data into (from) a systolic array is addressed, in the same context as the synthesis problem. The primary constraint is that all I/0 must occur at boundary processors. It is shown that a simple linear condition imposed on the allocation function is necessary and sufficient to satisfy this constraint. This may involve augmenting the domain and introducing new dependencies into the algorithm. We describe how the original specification is to be augmented, how the new recurrence is to be analyzed, and finally how the target architecture and the control signals that govern the I/0 are to be derived within a single unified framework.