Mode analysis of logic programs is the derivation of the input/output relations of logic variables and their embedded terms. Mode information is critical in enabling many types of compiler optimizations, for example thread partitioning. It is therefore useful to derive modes automatically at compile time, without assistance from the programmer. In this thesis, an automatic mode analyzer is described, based upon a static-graph reduction technique. This extends the seminal work of Ueda and Morita by presenting an implementation algorithm and its empirical performance for a benchmark suite. It is shown that the first mode analyzer prototype produces correct results in reasonable time.